Let’s look at how we. 01 Simulation 환경 01장 SystemVerilog for Testbench 01. It supports all methods like copy, compare, clone, print, etc as discussed in the UVM object section. g. Because this will be created during the run_phase it can't extend uvm_component, and it wouldn't make sense for this class to have phases. . uvm_sequence_item class hierarchy As shown in the above diagram, uvm_sequence_item is derived from the uvm_transaction class. It can contain registers, register files, memories and sub-blocks. The reason being packet and packetD are type compatible, since packetD is an extension of packet. pyuvm uses cocotb to interact with the simulator and schedule simulation events. id = 42; At this point you might be tempted to call the object “t1”. logger. A utils macro should be used inside every user-defined class that extends uvm_object directly or indirectly, including uvm_sequence_item and uvm_component. They automatically create a new object via calls to `uvm_create, randomize the item and send it to a sequencer. Accellera UVM Tutorial 2016 is a comprehensive presentation that covers the basics and advanced features of the Universal Verification Methodology (UVM), a standard framework for creating reusable and portable verification components and environments. drop_objection (uvm_object obj = null, string description = ” “, int count = 1) Drops number of objections for corresponding object with default count = 1 The copy method does a copy of the mentioned object. Type can be scalar objects, class handles, queues, lists, or even virtual interfaces) cntxt is the hierarchical starting point of where the database entry is. Parameterized classes in the UVM must be registered using the uvm_object_param_utils macro as below: `uvm_object_param_utils (som_util# (entry_w)) For more background, please see my discussion on this topic. Inline constraints (i. S. Within a non-static class method, randomize() and this. The compare() method compares two objects to return 1 in case of successful comparison. Your sequence would have, instead of an array of pixels, an array of ints, and then you could transform from/to in the driver and monitor. For convenience, you can use the subtype, uvm_in_order_built_in_comparator # (T) for built-in types. `uvm_object_param_utils(TYPE) For parameterized objects, with field macros, use `uvm_object_param_utils_begin(TYPE) `uvm_field_* macro invocations here `uvm_object_utils_end Simple (non-parameterized) objects use the uvm_object_utils* versions, which do the following: Implements get_type_name, which returns TYPE as a. Objections provide a facility for coordinating status information between two or more participating. It has only one object in the entire simulation space. Blocking operationsPacking is just a way to convert your uvm_object into a bit array. That means the other parameter Tname of. Implement the callback method. UVM Object Pack/Unpack. A resource is any piece of information that is shared between more than one component or object. 1 Class Reference is a comprehensive document that describes the classes, methods, macros, and callbacks that constitute the UVM 1. Pack A class called Packet is defined with some variables to store address and data, and is registered with `uvm_field_int macros to enable automation. The create method internally makes a call to the factory to look up the requested type and then. Uvm_env. UVM Questions: What is the difference between UVM creat…UVM consists of three main types of UVM classes, uvm_object; uvm_transaction; uvm_component; uvm_object. Later on, we want to run the same set of tests created above, using the same transaction. It is then placed into the configuration database using uvm_config_db so that other testbench components within this environment can access the object and configure sub components accordingly. `uvm_create (Item/Seq) This macro creates the item or sequence. After new'ing , it uses set_name() to assign the appropriate value to the name string. Let’s discuss the macro-based approach in UVM sequence macro and existing methods approach in the uvm_sequence_base class methods section. this(this)) and obj. Its primary role is to define a set of methods for such common operations as create , copy, compare, print, and record . events. Alternatively, if the change is intended to be global, there is a default printer that automatically created at root called uvm_default_printer . Connect and share knowledge within a single location that is structured and easy to search. 01 Simulation 환경 01장 SystemVerilog for Testbench 01. 05 Data Arrays 01. trigger. The create function asks the UVM factory to create an object. You need to create an array of ral_block_traffic_cfg objects: rand ral_block_traffic_cfg cfg [2]; You created an array of type uvm_reg_block, named it ral_cfg, but it has nothing to do with the ral_block_traffic_cfg object. UVM_DEFAULT specifies. 2에서는 반드시 constructor를 기술하여야 한다. Blocks ¶. 3. Let’s call the record in our jelly bean scoreboard. Eventually, everything in UVM is derived from this base class, including uvm_sequence_item. The lack of typing means a lack of parameterized ports, exports, and uvm_tlm_fifos. base. The clone () method was declared in uvm_object and returns a handle of type uvm_object. sv and the many svh files for the class files (reg, tlm, macros, drivers. Divide the DB into smaller domains by grouping values into config objects. Posted November 30, 2015. UVM_WARNING @ 0: reporter [TPRGED] Type name 'packet2mem_comp_Str' already registered with factory. svh" endpackage. First, let's. The compare method returns 1 if comparison matches for the current object when it is compared with the R. The uvm_object_registry has static methods, which you call with the class::type_id::create() syntax. randomize with {…} or `uvm_do_with) permit specifying additional constraints when randomizing an object. package my_stuff; `include "Packet. In this page, we'll try to execute a sequence item using the start_item/finish_item task. The proxy enables efficient registration with the uvm_factory. Deploying Parameterized Interface with UVM Wayne Yun AMD, Inc. The update can be performed using the using the physical interfaces (frontdoor) or uvm_reg::poke () (backdoor) access. 03. 2 Class Reference is independent of any specific design processes and is complete for the construction ofThe UVM 1. So, a data class derived from uvm_sequence_item or uvm_component will have access to the print() function as well. The set_type_override() is another static function of the uvm_object_registry. Because this will be created during the run_phase it can't extend uvm_component, and it wouldn't make sense for this class to have phases. Typically configuration classes and data objects are derived from. uvm_env is used to create and connect the uvm_components like driver, monitors , sequeners etc. If you are looking to print the entire topology, create a uvm_table_printer in your base test, and then use it in your end_of_elaboration_phase to print your class heirarchy in table format. 2 User’s Guide. 01 SystemVerilog Testbench 구조 01. Before moving to uvm_sequence_item will look into uvm_object concepts required to write uvm_sequence_item, The uvm_object has a number of virtual methods that are used to implement common data object functions (copy, clone, compare, print, transaction, and recording) and these should be implemented to make the sequence_item more general purpose. This is a message generated by vcs: Error- [ICTTFC] Incompatible complex type usage Incompatible. By applying stimulus to the register model, the actual design registers will exhibit the changes applied by the stimulus. This class will also need to be able to get information from the config_db using hierarchical paths, and plain old uvm_objects don't have hierarchy. When used as a base for user-defined RegModel test sequences, this class provides convenience methods for reading and writing registers and memories. 2 User’s Guide. 1, the presence of such a constructor is not enforced by the library and they are technically optional. __init__() if you override the __init__() method in a uvm_component. It is extended from its parent class uvm_resource_dbMarch 24, 2021. The uvm_printer class provides an interface for printing uvm_object s in various formats (line 1). raise_objection (uvm_object obj = null, string description = ” “, int count = 1) Raises number of objections for corresponding object with default count = 1. In the UVM, there are mechanisms to automate the retrieval of data from the configuration database. as you can see from your log that isnt the case for IUS. When the factory is called upon to create an object. uvm_object like uvm_transaction is not connected to any particular DUT interface and its fields can take any random value based on randomization constraints. pyuvm implements the most often-used parts of the UVM while taking advantage of the fact that Python does not have strict typing and. SystemVerilog allows you to create modules and classes that are parameterized. It is a standardized methodology for verifying digital designs and systems-on-chip (SoCs) in the semiconductor industry. data = 2; t1. ” )The utility macro `uvm_object_utils registers this class with the factory, which we will discuss later, and allows access to the create method which is needed for cloning. Add a comment. class tx_item extends uvm_sequence_item;. 1. User classes derived directly from uvm_void inherit none of the UVM functionality, but. A policy object can be passed along to set parameters like depth of comparison, verbosity, maximum number of. This behavior is called “overriding” and there are 2 types of overriding is possible with UVM Factory (described below). The UVM methodology enables engineers to quickly develop powerful,. Share. uvm_config_db# (rx_agent_cfg)::get (null, "uvm_test_top. 1. In this post, let’s think of it as a global associative array where the keys are strings of event names, and the values are the uvm_event objects. For objects, pack 4 bits prior to packing the object itself. Define your virtual method, for example wait_state, but leave it empty. A parent creates a child, and the uvm_component represents a hierarchal family tree in a database. For example: `define STR (str) `"str`". UVM provides a transaction class that can be extended to create transaction objects that carry information between the DUT and the testbench. event_object_h =. UVM stands for U niversal V erification M ethodology. pyuvm is the Universal Verification Methodology implemented in Python instead of SystemVerilog. The uvm_object class is the base class for all UVM data and hierarchical classes. This flexibility allows comprehensive testing of different configurations using a single, reusable testbench, significantly reducing development time and effort. Then you can do: typedef uvm_object_registry# (abc_test_seq,`STR (`SEQ_NAME (abc))) type_id;. If no constructor is specified, a default constructor is. Refer to “Macros” in the UVM 1. The uvm_comparer adds up policy for the comparison and counts the number of miscompares if any. Each component you create has a handle to its parent, and the parent has a list of handles that are its children. A cleaner implementation would have been for uvm_component_registry to be its own class, that doesn’t extend uvm_object_wrapper, that instead creates an instance of a uvm_object_wrapper and registers it with the factory instead of itself. Follow. To avoid the overhead of creating an instance of every component and object that get registered, the factory holds lightweight wrappers, or proxies. Uvm factory is one of the most notable term when using uvm methodology. These work predictably with non-parameterized classes as shown here. We are then calling the "set_finish_on_completion" method. Aside from registering a class with the factory, we've seen that the. To maintain uniformity in naming the components/objects, all the. UVM utility & field macros. We would like to show you a description here but the site won’t allow us. . 02. `uvm_create (Item/Seq) This macro creates the item or sequence. The factory (or to be precise, uvm_component_registry) will call new on behalf of you. event_object_h =. uvm event callbacks are an alternative to using processes that wait on events. object queues and publishes a number of transfers equal to the total length of the burst size. This is known as the UVM factory override mechanism. No string-based lookup support for multiple types with the same type name. “value” is the actual object handle shared through the uvm_config_db. randomize with {…} or `uvm_do_with) permit specifying additional constraints when randomizing an object. We remember the file and line number, and the calling context (the. The UVM application programming interface (API) defines a standard for the creation, integration, and extension of UVM Verification Components (UVCs) and verification environments that scale from block to system. 03 Operators 01. TYPE’s constructor, if defined, must have default values on all it arguments. Bases: uvm. B. method_call() is really method_call(. A function cannot have time controlled statements like @, #, fork join, or wait; A function cannot start a task since tasks are allowed to consume. Is this achievable in UVM 1. Typically configuration classes and data objects are derived from this class and are passed to different testbench components during the course of a simulation. Try these examples yourself. There is often a need to copy, compare and print values in these classes. It is the base class for all UVM data and hierarchical classes. This makes them more flexible, and able to work on a range of data types instead of just a single one. uvm_object. Supposed that your component name is "comp" in ENV, and the env is named "env" in the uvm_test, so in test bench top module, you should use below code to get the configuration handle. These macros can appear anywhere in the declaration space of the class declaration of T and will associate the string S to the object type T. Line 11-Line 15 Use the UVM functions to automatically implement functions such as copy(), compare(), print(), pack(), and so on. So UVM phases act as a synchronizing mechanism in the life cycle of a simulation. 2? I tried the following, which looked like it may work. Object and component types are registered with the factory using lightweight proxies to the actual objects and components being created. These Subtypes include uvm_printer, uvm_line_printer, uvm_tree_printer, uvm_table_printer. の間に挟んで使うマクロです。. This is known as the UVM factory override mechanism. 05 Data Arrays 01. uvm_reg_block. uvm_component::set_inst_override (relative_inst_path, original_type_name, override_type_name) The fourth method is using the set_inst_override function of the uvm_component. `uvm_object_param_utils_begin. Both the main sequence and the other sequence get an uvm_event with. メンバの型によって、さまざまあります。. Use uvm_config_db# (uvm_object)::set. Bases: object. event_object event_object_h; uvm_object temp_obj; . this(obj)). The usage of Factory involves three steps. For example: `define STR (str) `"str`". Using automation macros. The uvm_analysis_port is a specialized TLM based class whose interface consists of a single function write () and can be embedded within any component as shown in the snippet below. Read more: UVM Object [uvm_object] In my last post, I recommended that you give every SystemVerilog object either a unique ID or name. We have seen put and get methods to operate with only one outstanding transaction at a time i. On the other side, Static component are physical components which are present since the begining and. Jun 20, 2014 at 15:13. So, a data class derived from uvm_sequence_item or uvm_component will have access to the print() function as well. To avoid the overhead of creating an instance of every component and object that get registered, the factory holds lightweight wrappers, or proxies. Previous Article. uvm_object is the one of the base classes from where almost all UVM classes are derived. Use uvm_field_int because as far as SystemVerilog is concerned, time is just an alias for longint. It is. 0a version of the standards document: “The goal is to allow stimulus and tests, including coverage and results checking, to be. With Easier UVM, configuration parameters should be accesed by calling uvm_config_db # (T)::get. 02. You can use the uvm_object_registry (T,S) or uvm_component_registry (T,S) registration macros. It is an abstract class with no data members or functions. Steps to create a UVM environment. class my_driver. Classes derived from uvm_object must implement the pure virtual methods such as create. You need a uvm_sequencer with seq_item_export to connect to the driver's seq_item_port. There are two ways to register an object with the UVM factory. e it is allowed to send the transaction Only after consumption of the previously sent transaction, in this case, the sender and receiver must be in sync else. Posted November 30, 2015. They are implemented separately from uvm_object so that users can plug in different ways to print, compare, etc. uvm_object is basically the main class. It makes sense to include print features in uvm_object so that all child classes will automatically gain access to those features. See Usage section below for information on using uvm_component_registry. UVM 1. 01 SystemVerilog Testbench 구조 01. Memory abstraction base class. Core class based operational methods (create, copy, clone, compare, print, record, etc. METHOD – callback method call to invoke. Uvm factory allow us to replace an uvm object or component class with it’s child class with minimum code modification. UVM TestBench architecture. Please see Register Abstraction for how each property is packed. Similarly, in the second line, the all to the "uvm_root" static get method returns a reference to the top-level "uvm_root" object and we are calling the "set_timeout" method on that object. The handle to the uvm_resource object is stored in two kinds of uvm_queues. 2 Class Reference represents the foundation used to create the UVM 1. Blocks. uvm_object has both as seen in its constructor. As I understood for all items inherited from uvm_component, they all need uvm_component parent as part of constructor input argument. uvm_report_error(). This is usually best done during the build phase, because doing so allows the parameters to be used to control the building of lower-level components. Using Callback. typedef uvm_object_string_pool #(uvm_event #(uvm_object)) uvm_event_pool; We’ll go in detail of uvm_pool in another post. Please see Register Abstraction for how each property is packed. The utils macros define the infrastructure needed to enable the object/component for correct factory operation. UVM REPORTING The uvm_report_object provides an interface to the UVM reporting facility. To implement some important methods in classes and variables, UVM provides the UVM Macros. In order to create a user-defined sequence : Derive from uvm_sequence base class with a specified data object type. Pre-defined Verbosity Levels. 用途は、UVMの「オートメーション」機能を適用するために使います。. 0 using simple producer/consumer examples. The user can simply apply a different. Triggers the event, resuming all waiting processes. The clone () method was declared in uvm_object and returns a handle of type. EXECUTING A SEQUENCE ITEM — THE DRIVER. Abstract- SystemVerilog provides several mechanisms for layering constraints in an object. do_pack. Follow. This guide is a way to apply the UVM 1. The compare method returns 1 if comparison matches for the current object when it is compared with the R. In a previous article, print, do_print and use of automation macros to print were discussed. 01 Building blocks in SystemVerilog [email protected] to use the UVM configuration facility? Configuration values are set in the uvm_config_db class using the set() method and retrieved using the get() method. This process is shown in the code below:Based on command line arguments like +link_speed and +lanes, a same set of test sequences can be run with all possible configurations. Each resource has a set of scope. Macro. UVM objects are. by The Art of Verification. Don’t confuse the class variable and the object. In the begin-end block the driver calls seq_item_port. `uvm_do (Item/Seq) This macro takes seq_item or sequence as argument. The recommended method in UVM for creating components or transaction objects is to use the built-in method::type_id::create () instead of calling the constructor new () directly. 02. The uvm_component_registry class extends uvm_object_wrapper and implements its create_component() function, but it also has many other functions related to registering itself with the factory and handling type overrides. It can be constructed from many different places, but normally a test might construct sequences and then run them – they embody the test. class my_test extends uvm_test uvm_table_printer m_printer; //. It allows for generic containers of objects to be created, similar to a void pointer in the C programming language. The utility macro `uvm_object_utils registers this class with the factory, which we will discuss later, and allows access to the create method which is needed for cloning. Also, uvm_pool is a singleton class , that explains why it has global access. We’ve already talked about how the factory uses uvm_object_wrappers to perform the actual creation and maps type names to such objects. This solution randomize the knobs, not the sequence (ie. UVM Field Macros. The singleton instance of uvm_coreservice_t provides a common point for all central uvm services such as uvm_factory, uvm_report_server and so on. Steps involved are, Write callback class. virtual class uvm_component extends uvm_report_object; uvm_component class definition provides many functions and tasks that are used to find, build, connect, and configure. March 24, 2021. Registration: While defining a class , its type has to be registered with the uvm factory. It is an abstract class with no data members or functions. The left-hand-side `lhs` and right-hand-side `rhs` objects are the two objects used for comparison. uvm_env is extended from uvm_component and does not contain any extra functionality. uvm_object The primary role of uvm_object class is to define a set of common utility functions like print, copy, compare and record which can be availed by any other class in a UVM testbench to save effort. If you are using OVM/UVM then get_full_name() / get_name() will return the name of the component in the testbench hierarchy. uvm_reg::update. This method calls uvm_event_base::wait_trigger followed by get_trigger_data. My last attempt was to declare an array of class inside my uvm_env class like:Make UVM_OBJECT_MUST_HAVE_CONSTRUCTOR the default behavior: Why uvm_object constructors are now mandatory: The UVM recommends that the following constructor be specified for any class extended from uvm_object: Backwards Compatibility: In UVM 1. `uvm_do (Item/Seq) This macro takes seq_item or sequence as argument. You should create a new macro that add quotes around it input argument. For transactions, the typical constructor is shown in Example 2. if you just declare the P2 as" My_Packet P2;" , the cast will work. Once unzipped, I see the source files with uvm. path","label",value) (Adding other objects into the uvm_config_db is just as straightforward as adding a virtual interface. Nearly all UVM classes are extended from uvm_object. It seems to me that the monitor class is missing from the scope of the soc_uvm_env in other words during compilation of soc_uvm. It does a deep comparison. Alternatively, if the change is intended to be global, there is a default printer that automatically created at root called uvm_default_printer . For more efficient and more flexible implementation, we can use user definable do_*() hooks. 02 SystemVerilog 기초 1 01. S. TYPE’s constructor, if defined, must have default values on all it arguments. Intro. UVM에서는 reusable testbench를 강조하는데, 이때 많은 configuration field들을 가진 config class를 작성하여 agent와 내부의 driver, sequencer, monitor등에서 사용한다. The create method internally makes a call to the factory to look up the requested type and then. On calling `uvm_do () the above-defined 6 steps will be executed. That means the other parameter Tname of. There are two branches in the hierarchy : Under uvm_component: Classes that define verification components like driver, monitor and. This method calls uvm_event_base::wait_ptrigger followed by. These macros form a block in which `uvm_field_* macros can be placed. callback in uvm_sequence. UVMFactory [source] ¶. 그래서 uvm_phase는 uvm_object 클래스를 이용해 시뮬레이션 시작, 끝을 결정합니다. e. It helps increase flexibility and resuability of our testbench. Place the callback hook. The UVM agent is a hierarchical component that groups together other verification components that are dealing with a specific DUT interface. UVM TestBench to verify Memory Model. Overriding a type involves the following steps: Firstly, the. uvm_reg_sequence. Testbench diagram. All counts are cleared and the any processes waiting on a call to wait_for(UVM_ALL_DROPPED, uvm_top) are released. This port contains a list of analysis exports that are connected to it. This can be useful for peak and off-peak times. So long as the Register Predictor receives a uvm_reg_bus_op object for eachThe TLM FIFO provides storage for the transactions between two independently running processes. For simple objects with no field macros, use `uvm_object_utils(TYPE) For simple. uvm_event_pool is a pool that stores the uvm_events. The reason why case 1 fail is that you "new" P2, which means the P2 is instantiated, so it is not only a handle. After all, you just set the value of data and id with the name “t1”. But, virtual_sequence and virtual_sequencer do not require any virtual keyword. This concept is widely used in UVM, especially the uvm_config_db configuration database. Objects of this type will be used by sequences. . get_type_name isn't intended to print the name of a type. 3. The uvm_object class is the base class for all UVM data and hierarchical classes. For transactions, the typical constructor is shown in Example 2. Jun 20, 2014 at 15:54. We would like to show you a description here but the site won’t allow us. We need to plan for it by structuring our code in certain ways. The uvm_event class is directly derived from the uvm_object class. Hence, it is required to have proper synchronization to avoid objects/components being called before they are created, The UVM phasing mechanism serves the purpose of synchronization. Q&A for work. After the utility macro are the field automation macros in the form ‘uvm_field_*(data member, flag). 1. This section defines the proxy component and object classes used by the factory. UVM Object and UVM Component. uvm_do_obj_callbacks(T, CB, OBJ, METHOD) It is similar to `uvm_do_callbacks macro, but it has an additional OBJ argument to specify external object associated with the. UVM pre-defines six verbosity levels; UVM_NONE to UVM_DEBUG. Now we are going to look at the next step, the Universal Verification Methodology (UVM) implemented in Python. class uvm_object; function new (string name); m_inst_id = m_inst_count++; m_leaf_name = name; endfunction endclass. Implement the function "create()" `define m_uvm_object_create_func(T) function uvm_object create (string name=""); T tmp; `ifdef. Not sure how that is going to help. This improves flexibility and scalability of testbench. This section defines the proxy component and object classes used by the factory. It allows for generic containers of objects to be created, similar to a void pointer in the C programming language. uvm_object has many common functions like print, copy and compare that are available to all its child classes and can be used out of the box if UVM automation macros are used inside the class definition. The handle to the uvm_resource object is stored in two kinds of uvm_queues. This method calls uvm_event_base::wait_trigger followed by get_trigger_data. uvm_object::create method allocates a new object of the same type as this object and returns it via a base uvm_object handle. sv is included. What is uvm_pool. It serves an important role to define a set of methods such as create, copy, print, clone, compare, record, etc. 02 Data Types 01. In order to understand the different role that the Accellera Portable Test and Stimulus (PSS) standard plays versus UVM, let's consider this brief statement about what PSS is intended to accomplish, taken from the 1. UVM_Object. The rest of the set_ get_ pairs provide access to the internal uvm servicesUVM uses the concept of a factory where all objects are registered with it so that it can return an object of the requested type when required. Universal Verification Methodology UVM Introduction The Accellera Universal Verification Methodology (UVM) is a standard verification methodology that includes a set of class libraries for the development of a verification environment. Description. A uvm_queue is created for every unique field_name. Factory is a centralized location to make calls from look-up tables for creation of any transaction types. All the signals listed as the module ports belong to APB specification. Specialization #(virtual xbus_ifc) the data type of the value, which here is a virtual Xbus interface handle. The important thing to remember is that each entry needs a unique field name or label (if the global scope is being used), or the path needs to1 Answer. What happens when both handles point to same object ? If we assign pkt to a new variable called pkt2, the new variable will also point to the contents in pkt. A flat uvm_config_db with wildcard scopes and many entries can be a performance hog. We would like to show you a description here but the site won’t allow us. Implementations of uvm_object::do_pack and uvm_object::do_unpack should regard this bit when performing their respective operation. If you haven't included the file "monitor. uvm_object - Data structures for testbench configuration; uvm_transaction - Stimulus generation & analysis; The values of the arguments of new method are used to create an entry in a linked list which the UVM uses to locate uvm_components in a pseudo hierarchy, this list is used in the messaging and configuration mechanisms. There are many kinds of design patterns. the reason for this is that for IUS the m_inst_id is being set to the. I guess the name "automation" is used, because they automatically write code so you don't have to. uvm_config_db#(TYPE)::set(this,"*. System Verilog has virtual methods, virtual interfaces, and virtual classes. Built in types (such as ints, bits, logic, and structs) can be compared using the default values for comp_type, convert, and pair_type. The first three methods above take uvm_object_wrapper as their type argument (s). Interfaces can contain tasks, functions, parameters, variables, functional coverage, and assertions. Step #1: Create a base callback class. It is registered with the factory using `uvm_object_utils because it is a transaction item; The main stimulus is written within the body() task, while pre_body() and post_body() are useful callbacks to be used if required; A data packet is created and sent for execution using `uvm_do macro; pre_body and post_body methods are not invoked in a. Unlike registers, memories are not mirrored because of the potentially large data space: tests that walk the entire memory space would negate any benefit from sparse memory modelling techniques. Sometimes a uvm_object is only needed by 1 other uvm_component, so, following object-oriented theory, we should use nested/inner classes.